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dual timing circuit the mc3456 dual timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. additional terminals are provided for triggering or resetting if desired. in the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor per timer. for astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor per timer. the circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 ma or drive mttl circuits. ? direct replacement for ne556/se556 timers ? timing from microseconds through hours ? operates in both astable and monostable modes ? adjustable duty cycle ? high current output can source or sink 200 ma ? output can drive mttl ? temperature stability of 0.005% per c ? normally aono or normally aoffo output ? dual version of the popular mc1455 timer on semiconductor ? semiconductor components industries, llc, 2001 august, 2001 rev. 3 1 publication order number: mc3456/d device operating temperature range package mc3456 semiconductor technical data dual timing circuit ordering information mc3456p ne556d 0 to +70 c plastic dip so14 pin connections p suffix plastic package case 646 d suffix plastic package case 751a (so14) (top view) discharge a threshold a control a reset a output a trigger a gnd v cc discharge b threshold b control b reset b output b trigger b 1 2 3 4 5 6 78 9 10 11 12 13 14 figure 1. 22 second solid state time delay relay circuit figure 2. block diagram (1/2 shown) figure 3. general test circuit test circuit for measuring dc parameters (to set output and measure parameters): a) when v s 2/3 v cc , v o is low. b) when v s 1/3 v cc , v o is high. c) when v o is low, pin 7 sinks current. to test for reset, set v o high, c) apply reset voltage, and test for current flowing into pin 7. when reset c) is not in use, it should be tied to v cc . 1.0 k load mt2 10 k 0.1 m f 0.01 m f 1 5 2 4 38 6 7 1.0 m f c 20 m g mt1 -10 v 1n4003 117 vac/60 hz 1n4740 3.5 k 250 v - + t = 1.1; r and c = 22 sec time delay (t) is variable by changing r and c (see figure 16). 10 m f v cc threshold control voltage trigger 2 (12) 3 (11) 6 (8) 5 k 14 5 k 5 k + - comp a + - comp b 7 gnd reset 4 (10) r s flip flop q inhibit/ reset 1 (13) 5 (9) discharge output r 1/2 mc3456 v r reset 4 8 i cc v cc 700 discharge 6 threshold 7 i th 2.0 k v s trigger 2 gnd 1 3 i sink i source v o 0.01 m f + 5 control voltage output v cc 1/2 mc3456
mc3456 http://onsemi.com 2 maximum ratings (t a = +25 c, unless otherwise noted.) rating symbol value unit power supply voltage v cc +18 vdc discharge current i dis 200 ma power dissipation (package limitation) p suffix, plastic package, case 646 derate above t a = +25 c d suffix, plastic package, case 751 derate above t a = +25 c p d 625 5.0 1.0 8.0 mw mw/ c w mw/ c operating ambient temperature range t a 0 to +70 c storage temperature range t stg 65 to +150 c electrical characteristics (t a = +25 c, v cc = +15 v, unless otherwise noted.) characteristics symbol min typ max unit supply voltage v cc 4.5 16 v supply current v cc = 5.0 v, r l = v cc = 15 v, r l = low state, (note 1) i cc 6.0 20 12 30 ma timing error (note 2) monostable mode (r a = 2.0 k w ; c = 0.1 m f) initial accuracy drift with temperature drift with supply voltage astable mode (r a = r b = 2.0 k w to 100 k w ; c = 0.01 m f) initial accuracy drift with temperature drift with supply voltage 0.75 50 0.1 2.25 150 0.3 % ppm/ c %/v % ppm/ c %/v threshold voltage v th 2/3 xv cc trigger voltage v cc = 15 v v cc = 5.0 v v t 5.0 1.67 v trigger current i t 0.5 m a reset voltage v r 0.4 0.7 1.0 v reset current i r 0.1 ma threshold current (note 3) i th 0.03 0.1 m a control voltage level v cc = 15 v v cc = 5.0 v v cl 9.0 2.6 10 3.33 11 4.0 v output voltage low (v cc = 15 v) i sink = 10 ma i sink = 50 ma i sink = 100 ma i sink = 200 ma (v cc = 5.0 v) i sink = 5.0 ma v ol 0.1 0.4 2.0 2.5 0.25 0.25 0.75 2.75 0.35 v output voltage high (i source = 200 ma) v cc = 15 v (i source = 100 ma) v cc = 15 v v cc = 5.0 v v oh 12.75 2.75 12.5 13.3 3.3 v toggle rate r a = 3.3 k w , r b = 6.8 k w , c = 0.003 m f (figure 17, 19) 100 khz discharge leakage current i dis 20 100 na rise time of output t olh 100 ns fall time of output t ohl 100 ns matching characteristics between sections monostable mode initial timing accuracy timing drift with temperature drift with supply voltage 1.0 10 0.2 2.0 0.5 % ppm/ c %/v notes: 1. supply current is typically 1.0 ma less for each output which is high. 2. tested at v cc = 5.0 v and v cc = 15 v. 3. this will determine the maximum value of r a + r b for 15 v operation. the maximum total r = 20 m w .
mc3456 http://onsemi.com 3 25 c i sink (ma) i sink (ma) v cc , supply voltage (vdc) i sink (ma) i source (ma) figure 4. trigger pulse width v t(min) , minimum trigger voltage (x v cc = vdc) figure 5. supply current figure 6. high output voltage figure 7. low output voltage (@ v cc = 5.0 vdc) figure 8. low output voltage (@ v cc = 10 vdc) figure 9. low output voltage (@ v cc = 15 vdc) 0.4 150 125 100 75 50 25 0 pw, pulse width (ns min) i cc , supply current (ma) 1.0 1.0 v cc -v oh (vdc) v ol , (vdc) 0.3 0.2 0.1 0 70 c 25 c 10 8.0 6.0 4.0 2.0 0 15 5.0 10 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.0 5.0 10 20 50 100 25 c 5.0 v v cc 15 v 10 1.0 0.1 0.01 1.0 2.0 5.0 10 20 50 100 2.0 5.0 10 20 50 100 10 1.0 0.1 0.01 1.0 2.0 5.0 10 20 50 100 10 1.0 0.1 0.01 25 c 0 c 25 c v ol , (vdc) v ol , (vdc) 25 c
mc3456 http://onsemi.com 4 t a , ambient temperature ( c) figure 10. delay time versus supply voltage v cc , supply voltage (vdc) figure 11. delay time versus temperature figure 12. propagation delay versus trigger voltage 5.0 0 v t(min) , minimum trigger voltage (x v cc = vdc) t d , delay time normalized t d , delay time normalized , propagation delay time (ns) t pd 1.015 1.010 1.005 1.000 0.995 0.990 0.985 01015 10 20 1.015 1.010 1.005 1.000 0.995 0.990 0.985 -75 -50 -25 0 25 50 75 100 125 300 250 200 150 100 50 0 0.1 0.2 0.3 0.4 0 c 70 c 25 c
mc3456 http://onsemi.com 5 figure 13. 1/2 representative circuit schematic 100 threshold comparator trigger comparator flip-flop output v cc threshold trigger reset discharge gnd discharge reset 100 k 5.0 k 5.0 k e c b 7.0 k 6.8k 3.9 k cb 220 4.7 k output control voltage 1.0 k 4.7 k 830 4.7 k 10 k 4.7 k 5.0 k general operation the mc3456 is a dual timing circuit which uses as its timing elements an external resistor/capacitor network. it can be used in both the monostable (one shot) and astable modes with frequency and duty cycle, controlled by the capacitor and resistor values. while the timing is dependent upon the external passive components, the monolithic circuit provides the starting circuit, voltage comparison and other functions needed for a complete timing circuit. internal to the integrated circuit are two comparators, one for the input signal and the other for capacitor voltage; also a flipflop and digital output are included. the comparator reference voltages are always a fixed ratio of the supply voltage thus providing output timing independent of supply voltage. monostable mode in the monostable mode, a capacitor and a single resistor are used for the timing network. both the threshold terminal and the discharge transistor terminal are connected together in this mode (refer to circuit figure 15). when the input voltage to the trigger comparator falls below 1/3 v cc the comparator output triggers the flipflop so that it's output sets low. this turns the capacitor discharge transistor aoffo and drives the digital output to the high state. this condition allows the capacitor to charge at an exponential rate which is set by the rc time constant. when the capacitor voltage reaches 2/3 v cc the threshold comparator resets the flipflop. this action discharges the timing capacitor and returns the digital output to the low state. once the flipflop has been triggered by an input signal, it cannot be retriggered until the present timing period has been completed. the time that the output is high is given by the equation t = 1.1 r a c. various combinations of r and c and their associated times are shown in figure 14. the trigger pulse width must be less than the timing period. a reset pin is provided to discharge the capacitor thus interrupting the timing cycle. as long as the reset pin is low, the capacitor discharge transistor is turned aono and prevents the capacitor from charging. while the reset voltage is applied the digital output will remain the same. the reset pin should be tied to the supply voltage when not in use.
mc3456 http://onsemi.com 6 figure 14. time delay c, capacitance ( f) m 100 10 1.0 0.1 0.01 0.001 10 m s 100 m s 1.0 ms 10 ms 100 ms 1.0 10 100 t d , time delay (s) figure 15. monostable circuit r l +v cc (5.0 v to 15 v) reset v cc 14 discharge 1 (13) 2 (12) threshold control voltage 0.01 m f 7 6 (8) trigger output 5 (9) 4 (10) r a r l c 3 (11) gnd 1/2 mc3456 pin numbers in parenthesis ( ) indicate bchannel figure 16. monostable waveforms (r a = 10 k w , c = 0.01 m f, r l = 1.0 k w , v cc = 15 v) t = 50 m s/cm figure 17. astable circuit control voltage 3 (11) r l +v cc (5.0 to 15 v) reset v cc 14 discharge 1 (13) 2 (12) threshold 0.01 m f 7 6 (8) trigger output 5 (9) 4 (10) r a r l c gnd 1/2 mc3456 r b t = 20 m s/cm (r a = 5.1 k w , c = 0.0 1 m f, r l = 1.0 k w , r b = 3.9 k w , v cc = 15 v) figure 18. astable waveforms
mc3456 http://onsemi.com 7 astable mode in the astable mode the timer is connected so that it will retrigger itself and cause the capacitor voltage to oscillate between 1/3 v cc and 2/3 v cc (see figure 17). the external capacitor char ges to 2/3 v cc through r a and r b and discharges to 1/3 v cc through r b . by varying the ratio of these resistors the duty cycle can be varied. the charge and discharge times are independent of the supply voltage. the charge time (output high) is given by: t 1 = 0.695 (r a +r b ) c the discharge time (output low) by: t 2 = 0.695 (r b ) c thus the total period is given by: t = t 1 + t 2 = 0.695 (r a + 2r b ) c the frequency of oscillation is then: f = 1 t = (r a +2r b ) c 1.44 and may be easily found as shown in figure 19. r a +2r b r b the duty cycle is given by: dc = to obtain the maximum duty cycle, r a must be as small as possible; but it must also be large enough to limit the discharge current (pin 7 current) within the maximum rating of the discharge transistor (200 ma). the minimum value of r a is given by: r a v cc (vdc) i 7 (a) v cc (vdc) 0.2 figure 19. free running frequency c, capacitance ( f) m 100 10 1.0 0.1 0.01 0.001 (r a + 2 r b ) 0.1 1.0 10 100 1.0 k 10 k 100 f, free running frequency (hz)
mc3456 http://onsemi.com 8 applications information tone burst generator for a tone burst generator, the first timer is used as a monostable and determines the tone duration when triggered by a positive pulse at pin 6. the second timer is enabled by the high output of the monostable. it is connected as an astable and determines the frequency of the tone. dual astable multivibrator this dual astable multivibrator provides versatility not available with single timer circuits. the duty cycle can be adjusted from 5% to 95%. the two outputs provide two phase clock signals often required in digital systems. it can also be inhibited by use of either reset terminal. (r a + 2r b ) c figure 20. tone burst generator figure 21. dual astable multivibrator r t trigger trigger trigger reset 4 discharge threshold 7 gnd 1/2 mc3456 14 v cc 5 output 10 reset 3 9 control 0.01 m f output 7 gnd 0.01 mf c2 14 v cc 13 discharge 12 threshold 8 11 control r b r a + 15 v gnd c1- r1 c1 reset 2 discharge 1 4 14 10 k 5 1n914 1n914 10 k 9 output trigger 10 reset +15 v r2 threshold 12 13 discharge c2 gnd 11 control voltage 0.001 8 output 0.001 output 6 37 gnd f = 0.91 (r1 + r2) c for c1 = c2 duty cycle r2 r1 + r2 t = 1.1 r t c1 f = 1.44 control voltage threshold trigger 1/2 mc3456 1/2 mc3456 1/2 mc3456 6 1 2
mc3456 http://onsemi.com 9 pulse width modulation if the timer is triggered with a continuous pulse train in the monostable mode of operation, the charge time of the capacitor can be varied by changing the control voltage at pin 3. in this manner, the output pulse width can be modulated by applying a modulating signal that controls the threshold voltage. test sequences several timers can be connected to drive each other for sequential timing. an example is shown in figure 24 where the sequence is started by triggering the first timer which runs for 10 ms. the output then switches low momentarily and starts the second timer which runs for 50 ms and so forth. figure 22. pulse width modulation waveforms figure 23. pulse width modulation circuit t = 0.5 ms/cm (r a = 10 kw, c = 0.02 mf, v cc = 15 v) +v cc (5.0 v to 15 v) r l 4 (10) reset v cc 14 r a discharge 1 (13) threshold 2 (12) control 3 (11) c modulation input output 5 (9) trigger 6 (8) output clock input gnd 7 1/2 mc3456 modulation input voltage 5.0 v/cm clock input voltage 5.0 v/cm output voltage 5.0 v/cm capacitor voltage 5.0 v/cm figure 24. sequential timing circuit 9.1 k threshold v cc reset 27 k 9.1 k v cc reset 27 k 50 k v cc reset control output load gnd gnd load 5.0 m f 0.001 m f gnd trigger discharge 1.0 m f control output 0.01 m f 0.001 m f threshold threshold discharge trigger 5.0 m f 0.01 m f discharge trigger load v cc (5.0 v to 15 v ) 0.01 m f control output 1/2 mc3456 1/2 mc3456 1/2 mc3456
mc3456 http://onsemi.com 10 package dimensions p suffix plastic package case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc3456 http://onsemi.com 11 package dimensions d suffix plastic package case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc3456 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc3456/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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